Search Results

You are looking at 1 - 2 of 2 items for

  • Author or Editor: Kumar Raj x
  • Refine by Access: Content accessible to me x
Clear All Modify Search
Mathematica Pannonica
Tilak Raj Sharma
Hitesh Kumar Ranote

In this paper, we introduce the notion of a Gel’fand Γ-semiring and discuss the various characterization of simple, k-ideal, strong ideal, t-small elements and additively cancellative elements of a Gel’fand Γ-semiring R, and prove that the set of additively cancellative elements, set of all t-small elements of R and set of all maximal ideal of R are strong ideals. Further, let R be a simple Gel’fand Γ-semiring and 1 ≠ tR. Let M be the set of all maximal left (right) ideals of R. Then an element x of R is t-small if and only if it belongs to every maximal one sided left (right)ideal of R containing t.

Open access


Most error-resilient media processing applications use multipliers as their basic building blocks. These are power-consumption and computationally intensive modules. In the existing works, several types of the multipliers were used to improve the hardware capacity, but those methods did not provide sufficient results. Therefore, in this manuscript, a Baugh-Wooley Multiplier design using Multiple Control Toffoli (MCT) and Multiple Control Fredrick gate (MCF) Reversible Logic gate (BWM-MCT-MCF) will be analyzed. Initially, Reversible Full Adder (RFA) is designed using Multiple Control Toffoli and Multiple Control Fredrick gate Reversible Logic gates. Then the proposed Reversible Full Adder is used in Baugh-Wooley Multiplier. By this, it reduces the hardware complexity with higher speed, lower area, lower power consumption. The proposed BWM-MCT-MCF multiplier is implemented in MATLAB, its performance shows lower Garbage output 22.78%, 24.88%, 20.95% compared with the existing designs, like BWM-FG-FRG, BWM-RL-TG, BWM-TG-FG respectively. Then the designed BWM-MCT-MCF is implemented using Xilinx ISE tool with the Virtex 5 device. From this, the performance of the proposed FPGA-BWM-MCT-MCF method shows lower delay 23.77%, 16.86% compared with the existing designs, like FPGA-BWM-RL-TG, FPGA-BWM-TG-FG respectively.

Open access