Baugh-Wooley Multiplier design using Multiple Control Toffoli and Multiple Control Fredkin reversible logic gates

K. Saritha Raj; P. Rajesh Kumar; M. Satyanarayana

doi:10.1556/1848.2022.00550

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International Review of Applied Sciences and Engineering

Volume/Issue:: Accepted Manuscript / Online First

Baugh-Wooley Multiplier design using Multiple Control Toffoli and Multiple Control Fredkin reversible logic gates

Authors:

K. Saritha Raj

K. Saritha RajDepartment of Electronics and Communication Engineering, Jawaharlal Nehru Technological University, Kakinada, Andhra Pradesh, India

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sarithakuchipudi@gmail.com

P. Rajesh Kumar

P. Rajesh KumarDepartment of Electronics and Communication Engineering, Andhra University College of Engineering, Visakhapatnam, India

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profprajeshkumar@gmail.com https://orcid.org/0000-0002-4279-799X

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M. Satyanarayana

M. SatyanarayanaDepartment of Electronics and Communication Engineering, MVGR College of Engineering, Vizianagaram, Andhra Pradesh, India

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Online Publication Date:: 02 Mar 2023

Publication Date:: 02 Mar 2023

Article Category:: Research Article

DOI:: https://doi.org/10.1556/1848.2022.00550

Keywords:: Baugh-Wooley Multiplier; Multiple Control Toffoli (MCT); Multiple Control Fredrick gate (MCF); reversible logic gates; Reversible Full Adder (RFA)

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Abstract

Most error-resilient media processing applications use multipliers as their basic building blocks. These are power-consumption and computationally intensive modules. In the existing works, several types of the multipliers were used to improve the hardware capacity, but those methods did not provide sufficient results. Therefore, in this manuscript, a Baugh-Wooley Multiplier design using Multiple Control Toffoli (MCT) and Multiple Control Fredrick gate (MCF) Reversible Logic gate (BWM-MCT-MCF) will be analyzed. Initially, Reversible Full Adder (RFA) is designed using Multiple Control Toffoli and Multiple Control Fredrick gate Reversible Logic gates. Then the proposed Reversible Full Adder is used in Baugh-Wooley Multiplier. By this, it reduces the hardware complexity with higher speed, lower area, lower power consumption. The proposed BWM-MCT-MCF multiplier is implemented in MATLAB, its performance shows lower Garbage output 22.78%, 24.88%, 20.95% compared with the existing designs, like BWM-FG-FRG, BWM-RL-TG, BWM-TG-FG respectively. Then the designed BWM-MCT-MCF is implemented using Xilinx ISE tool with the Virtex 5 device. From this, the performance of the proposed FPGA-BWM-MCT-MCF method shows lower delay 23.77%, 16.86% compared with the existing designs, like FPGA-BWM-RL-TG, FPGA-BWM-TG-FG respectively.

Abstract

1 Introduction

Multiplication is an important function of arithmetic operations. High-speed multipliers are in higher demand all-time [1, 2]. Over the course of previous investigations, several energy-efficient multipliers have been successfully created [3, 4]. Reversible logic produces higher power consumption and a significant amount of energy dissipation because of information loss in standard design methods [5, 6]. The power usage and delay are critical in Digital signal processing (DSP) design and manufacturing, which are the primary design parameters of DSP devices for high-performance application [7, 8]. In the DSP application, the multiplier is critical. Depending on the multiplier circuits, certain applications, like Filtering (FIR, IIR), Fourier Transforms (FFT), and convolution are utilized. Multiplication is a common computer operation, but it is done on most processors, because it is time consuming and expensive [9–13]. There is a variety of different calculation problems that can be regulated by the speed at which they are carried out, and these are called “multiplication” [14, 15].

The development of digital circuits in the current digital era is constrained by research into alternative nano devices to CMOS technology [15-17]. The digital chips density is naturally raised as nano devices are produced in an effort to reduce power consumption and heat dissipation by this use. A number of methods were presented previously for improving the hardware capacity of the multipliers, but no one method provided sufficient results, because of lesser speed, power consumption, count of gates, garbage output, number of quantum costs are increased [18]. To overcome these issues, this work is proposed.

In this manuscript, reversible logic gates replace the half-adders and full-adders in the multiplier structure. This design uses two Reversible gates, such as Multiple Control Toffoli and Multiple Control Fredrick gate in place of a single reversible gate. It contains additional benefits for reducing the garbage being produced, which helps reduce the overall delay and power consumed by the RG. All previous designs had conceded to unwanted outputs, unwanted inputs, associated quantum cost. This manuscript concentrates on delay, garbage output, constant input, quantum costs and power calculation parameters. The proposed Baugh-Wooley Multiplier design using Multiple Control Toffoli and Multiple Control Fredrick gate Reversible Logic gates has shaved the depth of circuits and increased the speed considerably. The delay and power requirements in the reversible multiplier design are very low compared to the existing circuit designs.

The main contributions of this work are abridged below,

Initially, RFA is designed by MCT and MCF Reversible Logic gates.
RFA is utilized in Baugh-Wooley Multiplier.
By this, it reduces the hardware complexity with higher speed, lower area, lower power consumption.
The proposed BWM-MCT-MCF Multiplier is done in MATLAB.
The performance metrics, like Gate Constant inputs, Count, Garbage outputs, quantum cost are analyzed.
The performance of the proposed BWM-MCT-MCF approach is analyzed with the existing designs, like Baugh-Wooley Wallace tree multiplier with new architecture using Feyman gate (FG) and Fredkin gate (FRG) reversible logic (BWM-FG-FRG) [19], multipliers design utilizing Reversible logic with Toffoli Gate (BWM-RL-TG) [20], High speed low power multipliers depending on reversible logic Toffoli Gate (TG) and Feyman gate (FG) (BWM-TG-FG) [21], respectively.
Then the designed BWM-MCT-MCF is implemented using Xilinx ISE tool with the Virtex 5 device.
The performance metrics, such as power, delay are examined.
The performance of the proposed FPGA-BWM-MCT-MCF approach is analyzed with the existing designs, like multipliers design utilizing Reversible logic with Toffoli gate (FPGA-BWM-RL-TG) [20], Higher speed lower power multipliers based on reversible logic (FPGA-BWM-TG-FG) [21].

The rest of this manuscript is structured as: section 2 deliberates the recent related works, section 3 explains the proposed design, section 4 demonstrates the results with discussion, section 5 concludes this manuscript.

2 Literature survey

Among the numerous studies based on Baugh-Wooley multiplier design, the recent works are described here.

Raveendran et al., [19] have presented BWM tree multiplier using reversible logic. The presented method was designed with the help of RFA circuit, multiple control Feynman and Fredrick reversible gate. The performance of the presented method was examined by gate count, quantum cost, garbage output, ancilla input. But the delay was increased.

Autade et al., [20] presented a multipliers design utilizing Reversible Logic with Toffoli gates. For designing the Baugh-Wooley Multiplier, first the full adder circuit using the multiple controlled reversible gates was designed. The reversible full adder was structured by the Reversible Logic and Toffoli gates. The structured full adder was used to design the Baugh-Wooley Multiplier. The number of gate count was decreased, but delay was increased.

Barati [21] has presented a higher speed lower power multipliers depending on reversible logic methods. The Reversible Half Adder, the Reversible Full Adder, the Dual Key gate, and the Kogge Stone Adder were designed using multiple control Toffoli gate and the Feynman gate. Then the designed half adder was used to design the Baugh-Wooley. But, the power was reduced, number of gate count was increased.

Rajmohan and Maheswari [22] have presented Compact Baugh-Wooley Multiplier Utilizing Reversible Logic. To design the full adder circuit, multiple controlled Toffoli reversible gates were used. The designed 5 × 5 reversible multiplier cell (full adder) was useful in designing Baugh-Wooley multiplier. The 5 × 5 reversible multiplier cell (full adder) was used, so that the number of gate count was decreased but the hardware complexity was increased.

Gudivada and Sudha [23] have presented BWM design in quantum-dot cellular automata utilizing 1-bit full adder with power dissipation analysis depending on reversible logic gates. The quantum-dot cellular automata using 1-bit full adder was designed by logic gates for reducing the area and the number of gate count. Then the designed 1-bit full adder was employed to BWM design and the quantum costs were reduced. The gate count was reduced but the speed was decreased.

3 Proposed design

The Baugh-Wooley Multiplier design using Multiple Control Toffoli and Multiple Control Fredrick gate Reversible Logic gates is proposed in this manuscript. Initially, RFA is designed utilizing MCT and MCF Reversible Logic gates. Then the proposed Reversible Full Adder is used in Baugh-Wooley Multiplier. By this, it reduces the hardware complexity with higher speed, lower area, and lower power consumption.

3.1 Reversible Full Adder design using MCT and MCF

The design of RFA is represented in Fig. 1. It consists of four inputs and four outputs, the inputs are A, B, C, 0 and the outputs are sum, carry, two garbage outputs, 0 is represented as the Ancilla inputs (constant inputs). While using these reversible gates, the delay of the architecture is decreased. The output sum and carry equations of RFA is given in equation (1 and 2).

S u m = A \oplus B \oplus C_{i n}

(1)

C a r r y = {(A \oplus B) C_{i n}} \oplus (A B)

(2)

The proposed RFA is used for designing the BWM. Figure 2 shows the BWM design using RFA. The RFA circuits in the Baugh Wooley Multiplier are represented in white and pink cells. The cell representation of white cell is depicted in Fig. 3 and the cell representation of pink cell is depicted in Fig. 4. In this work, two reversible multiplier cells are represented: white and pink cells. The purpose and the difference of two cells are given: inside white cell AND gate is used and inside pink cells NAND gate is used. The white cells denote multiplier cell employed for the count of 2's complement. The pink cells denote multiplier cell. Here, every cell obtains 4 inputs that are, multiplicand input (vertical-pink line), multiplier input (horizontal-green line), sum from prior cells (diagonal-black line), carry from prior cells (vertical-black line). They create 2 outputs: sum output (diagonal-black line), carry output (vertical black line). Each cell has 4 inputs with 2 outputs, the reversible amplifier cell is constructed into a cell with 5 inputs as well as 5 outputs to maintain reversible multiplier cell. Among these, 3 outputs have remained as garbage outputs. These are defined as don't care outputs, because it may be left not mentioned, it leads to incomplete mentioned process.

They create 2 outputs: sum output (diagonal-black line), carry output (vertical black line).

This is performed based on the following example: Let the counts be multiplied by $A a n d B$ . Wherein $A$ implies $m - b i t$ multiplier, $B$ implies $m - b i t$ multiplicand, $A$ multiplier and $B$ multiplicand are used to perform the signed $m \times m$ multiplication without variation when the results have similar bit-width as inputs. For example: $- 2$ * $3$ is $- 6$ , its binary representation (0010)₂ × (0011)₂ = (1010)₂. What occurs if the outcome is in “ $2 m$ ” bits. Either needs to utilize sign extension or $2 m \times 2 m$ array multiplier. Baugh-Wooley multiplication is a proficient approach to deal in such situations.

The Baugh-Wooley has been developed for 2's-complement count. Consider two

m -

bit numbers,

C

and

D

to be multiplied.

C

and

D

are expressed in given equation (3 and 4),

C = - c_{m - 1} 2^{m - 1} + \sum_{j = 0}^{m - 2} c_{j} 2^{j}

(3)

D = - d_{m - 1} 2^{m - 1} + \sum_{i = 0}^{m - 2} d_{i} 2^{i}

(4)

here

c_{j}

and

d_{i}

are represented as bits in

C

and

D

respectively,

c_{m - 1}

and

d_{m - 1}

are represented as sign bits. The product is expressed in given equation (5 and 6),

P = C \times D

(5)

\begin{array}{l} P = c_{m - 1} d_{m - 1} 2^{2 m - 2} + \sum_{j = 0}^{m - 2} \sum_{i = 0}^{m - 2} c_{j} d_{i} 2^{j + i} \\ - 2^{m - 1} \sum_{j = 0}^{m - 2} c_{j} d_{m - 1} 2^{j} - 2^{m - 1} \sum_{i = 0}^{m - 2} c_{m - 1} d_{i} 2^{i} \end{array}

(6)

The above equation indicates that the final product is obtained by subtract the last 2 positive terms from the first 2 terms.

Assume

C

and

D

are 4-bit binary numbers, then the product

P = C \times D

is 8-bits long and is given in equation (7),

\begin{array}{l} P = c_{3} d_{3} 2^{6} + \sum_{j = 0}^{2} \sum_{i = 0}^{2} c_{j} d_{i} 2^{j + i} + 2^{3} \sum_{j = 0}^{2} \overline{d_{3} c_{j}} 2^{j} \\ + 2^{3} \sum_{i = 0}^{2} \overline{c_{3} d_{i}} 2^{i} - 2^{7} + 2^{4} \end{array}

(7)

Equation (7) is known as design of Baugh-Wooly Multiplier utilizing Reversible Full Adder with multiple control Toffoli and Fredrick gate. With the help of this algorithm, Baugh-Wooley Multiplier reduces delay, power consumption and the area.

4 Results and discussion

This section describes the Baugh-Wooley Multiplier design using Multiple Control Toffoli and Multiple Control Fredrick gate Reversible Logic gates. The simulation of proposed BWM-MCT-MCF multiplier design is done in MATLAB, PC along Intel Core i5, 2.50 GHz CPU, 8 GB RAM, Windows 7. The performance of the proposed BWM-MCT-MCF design is analyzed under certain performance metrics. The obtained results are compared with existing designs, such as BWM-FG-FRG, BWM-TG-FG, BWM-RL-TG.

4.1 Performance metrics

The performance of the proposed BWM-MCT-MCF design is analyzed with performance metrics, like constant inputs, garbage outputs, gate count, quantum cost.

4.1.1 Gate count and hardware complex

An important factor during design evaluation is to scale the reversible logic depending on the count of gates. It helps to find out the hardware complexity. But the proposed circuit proves that hardware complexity is better than existing approaches, because any logic (AND, OR, EXOR, NOR gates) in the design can be implemented within minute. So, the hardware complexity of the Baugh-Wooley Multiplier design is decreased.

4.1.2 Constant inputs

Garbage/constant input is the input that is utilized as control input through coupling either logical lower or higher for obtaining the desired operation in the output. The count of constant inputs is a key consideration of reversible logic circuit designing.

4.1.3 Garbage outputs

It indicates the count of reversible gate outputs that are not performing beneficial functions. Optimizing garbage output is another restriction on reversible logic circuit design.

Table 1 shows the performance analysis of the performance metrics. Here, Power, Delay, quantum cost are analyzed for determining the proposed BWM-MCT-MCF performance. The proposed approach attains 23.94%, 21.94%, 24.94% lower gate count; 25.75%, 16.86%, 33.86% lower constant input; 23.88%, 27.87%, 21.54% lower Garbage outputs; 15.88%, 21.65%, 32.54% lower Power consumption; 26.87%, 25.55%, 26.97% lower Delay; 26.87%, 21.33%, 20.66% lower Quantum cost are compared with the existing designs, such as BWM-FG-FRG, BWM-TG-FG, and BWM-RL-TG, respectively.

Table 1.

Performance analysis

Performance metrics	BWM-FG-FRG	BWM-TG-FG	BWM-RL-TG	BWM-MCT-MCF (Proposed)
Gate count	44	42	40	16
Constant inputs	52	44	42	12
Garbage outputs	52	50	49	28
Quantum cost	37	32	28	18

5 FPGA implementation of proposed Baugh Wooley multiplier

In this section, the implementation of the proposed BWM-MCT-MCF is discussed. Then the designed BWM-MCT-MCF is implemented using the Xilinx ISE tool with the Virtex 5 device along Intel (R) Core (TM) 2 Duo CPU T6600 @ 3.2 GHz, system. FPE320 is a 3U VPX FPGA processor board in Xilinx Virtex-5 FPGAs available with an FMC mezzanine site. The performance metrics, such as power and delay are analyzed. The reversible multiplier architectures are designed and implemented using the Xilinx ISE tool to calculate the delay. Xpower analysis tool is used to calculate the power. Then the performance of the proposed FPGA-BWM-MCT-MCF method is compared with the existing designs, like FPGA-BWM-RL-TG [20], FPGA-BWM-TG-FG [21].

Figure 5 shows the FPGA implementation of Baugh-Wooley Multiplier in Vertex 5 kit. Figure 6 displays the RTL Schematic of BWM. Figure 7 depicts the Simulation Result of BWM. Figure 8 portrays the Device utilization of BWM.

5.1 Performance analysis

The performance metrics, like power consumption, number of input LUTs, number of occupied slices, voltage, current and delay are analyzed.

Table 2 displays the performance analysis of the power consumption, number of input LUTs, number of occupied slices, voltage, current and delay for determining the proposed FPGA-BWM-MCT-MCF performance. Then the performance of the proposed method provides 15.88%, 21.65%, lower power consumption; 23.84%, 28.04% lower number of LUTs, 43.83%, 28.83%, number of occupied slices, equal voltage, 24.93%, 27.923% lower current consumption 26.87%, 25.55%, lower delay compared with the existing designs, such as FPGA-BWM-TG-FG, FPGA-BWM-RL-TG respectively.

Table 2.

Performance Analysis of delay and power

Performance metrics	Methods
Performance metrics	FPGA-BWM-TG-FG	FPGA-BWM-RL-TG	FPGA-BWM-MCT-MCF (Proposed)
Number of input LUTs	79	57	33
Number of occupied slices	77	53	18
Voltage	0.76W	0.76W	0.076W
Current Consumption	0.45A	0.65A	0.26A
Delay	178.34	169.03	89.10
Power consumption	729.33	684.45	515.12

6 Conclusion

The Baugh-Wooley Multiplier is successfully designed in this manuscript using Multiple Control Toffoli (MCT) and Multiple Control Fredrick gate (MCF) Reversible Logic gates. The proposed BWM-MCT-MCF multiplier is done in MATLAB. Finally, the proposed BWM-MCT-MCF method attains lower quantum cost 23.86%, 25.87%, 31.63% compared with the existing designs, like BWM-FG-FRG, BWM-RL-TG, BWM-TG-FG respectively. Then the designed BWM-MCT-MCF is implemented using the Xilinx ISE tool with the Virtex 5 device. Here, the proposed FPGA-BWM-MCT-MCF method attains lower power 32.75%, 15.86% compared with the existing designs, like FPGA-BWM-RL-TG, FPGA-BWM-TG-FG, respectively.

Funding

This research did not receive any specific grant from funding agencies in the public, commercial, or not-for-profit sectors.

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International Review of Applied Sciences and Engineering

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László POKORÁDI Óbuda University Budapest Hungary

Antal PUHL University of Debrecen Debrecen Hungary

Roman RABENSEIFER Slovak University of Technology in Bratislava Bratislava Slovak Republik

Mohammad H. A. SALAH Hashemite University Zarqua Jordan

Dietrich SCHMIDT Fraunhofer Institute for Wind Energy and Energy System Technology IWES Kassel Germany

Lorand SZABÓ Technical University of Cluj-Napoca Cluj-Napoca Romania

Csaba SZÁSZ Technical University of Cluj-Napoca Cluj-Napoca Romania

Ioan SZÁVA Transylvania University of Brasov Brasov Romania

Péter SZEMES University of Debrecen Debrecen Hungary

Edit SZŰCS University of Debrecen Debrecen Hungary

Radu TARCA University of Oradea Oradea Romania

Zsolt TIBA University of Debrecen Debrecen Hungary

László TÓTH University of Debrecen Debrecen Hungary

László TÖRÖK University of Debrecen Debrecen Hungary

Anton TRNIK Constantine the Philosopher University in Nitra Nitra Slovakia

Ibrahim UZMAY Erciyes University Kayseri Turkey

Tibor VESSELÉNYI University of Oradea Oradea Romania

Nalinaksh S. VYAS Indian Institute of Technology Kanpur India

Deborah WHITE The University of Adelaide Adelaide Australia

Sahin YILDIRIM Erciyes University Kayseri Turkey

International Review of Applied Sciences and Engineering
Address of the institute: Faculty of Engineering, University of Debrecen
H-4028 Debrecen, Ótemető u. 2-4. Hungary
Email: irase@eng.unideb.hu

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2021
Scimago
Scimago H-index	7
Scimago Journal Rank	0,199
Scimago Quartile Score	Engineering (miscellaneous) (Q3) Environmental Engineering (Q4) Information Systems (Q4) Management Science and Operations Research (Q4) Materials Science (miscellaneous) (Q4)
Scopus
Scopus Cite Score	1,2
Scopus CIte Score Rank	Architecture 48/149 (Q2) General Engineering 186/300 (Q3) Materials Science (miscellaneous) 79/124 (Q3) Environmental Engineering 118/173 (Q3) Management Science and Operations Research 141/184 (Q4) Information Systems 274/353 (Q4)
Scopus SNIP	0,457

2020
Scimago H-index	5
Scimago Journal Rank	0,165
Scimago Quartile Score	Engineering (miscellaneous) Q3 Environmental Engineering Q4 Information Systems Q4 Management Science and Operations Research Q4 Materials Science (miscellaneous) Q4
Scopus Cite Score	102/116=0,9
Scopus Cite Score Rank	General Engineering 205/297 (Q3) Environmental Engineering 107/146 (Q3) Information Systems 269/329 (Q4) Management Science and Operations Research 139/166 (Q4) Materials Science (miscellaneous) 64/98 (Q3)
Scopus SNIP	0,26
Scopus Cites	57
Scopus Documents	36
Days from submission to acceptance	84
Days from acceptance to publication	348
Acceptance Rate	23%

2019
Scimago H-index	4
Scimago Journal Rank	0,229
Scimago Quartile Score	Engineering (miscellaneous) Q2 Environmental Engineering Q3 Information Systems Q3 Management Science and Operations Research Q4 Materials Science (miscellaneous) Q3
Scopus Cite Score	46/81=0,6
Scopus Cite Score Rank	General Engineering 227/299 (Q4) Environmental Engineering 107/132 (Q4) Information Systems 259/300 (Q4) Management Science and Operations Research 136/161 (Q4) Materials Science (miscellaneous) 60/86 (Q3)
Scopus SNIP	0,866
Scopus Cites	35
Scopus Documents	47
Acceptance Rate	21%

International Review of Applied Sciences and Engineering
Publication Model	Gold Open Access
Submission Fee	none
Article Processing Charge	1100 EUR/article
Regional discounts on country of the funding agency	World Bank Lower-middle-income economies: 50% World Bank Low-income economies: 100%
Further Discounts	Limited number of full waiver available. Editorial Board / Advisory Board members: 50% Corresponding authors, affiliated to an EISZ member institution subscribing to the journal package of Akadémiai Kiadó: 100%
Subscription Information	Gold Open Access

International Review of Applied Sciences and Engineering
Language	English
Size	A4
Year of Foundation	2010
Volumes per Year	1
Issues per Year	3
Founder	Debreceni Egyetem
Founder's Address	H-4032 Debrecen, Hungary Egyetem tér 1
Publisher	Akadémiai Kiadó
Publisher's Address	H-1117 Budapest, Hungary 1516 Budapest, PO Box 245.
Responsible Publisher	Chief Executive Officer, Akadémiai Kiadó
ISSN	2062-0810 (Print)
ISSN	2063-4269 (Online)

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Abstract

Abstract

1 Introduction

2 Literature survey

3 Proposed design

3.1 Reversible Full Adder design using MCT and MCF

4 Results and discussion

4.1 Performance metrics

4.1.1 Gate count and hardware complex

4.1.2 Constant inputs

4.1.3 Garbage outputs

5 FPGA implementation of proposed Baugh Wooley multiplier

5.1 Performance analysis

6 Conclusion

Funding

References

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